The present invention relates to a gain control arrangement and to a method for controlling the gain of a variable gain amplifier in dependence on the difference between the actual magnitude and the desired magnitude of a read signal provided over an optical data carrier read channel.
To recover data from optical data carriers, it is known to class the write/read channel of the data carrier in accordance with a partial response characteristic which approximates to the frequency response characteristics of the channel, and the arrangement or design of a digital data recovery circuit is selected to optimise data recovery from a channel with that partial response characteristic.
If the signal from the head assembly is to be equalised to more closely assume the partial response class, the choice of whether an analogue or digital equalising filter is used depends on whether it is desired to position the filter before or after the flash analogue-to-digital convertor (ADC) used for sampling the read signal in the read path. Typical partial response (PR) characteristics are PR(a, b, a), where a and b are constants in the overall equalised channel impulse response of a+bD+aD.sup.2, and PR(a, b, b, a), where a and b are constants in the overall equalised channel impulse response of a+bD+bD.sup.2 +aD.sup.3. Here, D represents a unit delay operator.
The impulse response in combination with an appropriate coding scheme, such as for example 8, 16 efm+ or 1, 7 RLL, gives rise to a final stream of digital waveform samples which have a limited set of ideal values. For PR(a, b, a) channels there are four such levels whereas for PR(a, b, b, a) channels there are five. In optimally recovering data from channels of these and other types, the read signal is often operated on to be centred on an ADC code of zero, as the use of 2's complement digital schemes for data recovery is often preferred over other schemes. Following this centring, the read signal should be operated on by an automatic gain control (AGC) device which appropriately scales the amplitude of the read signal to allow optimum data recovery to be performed by way of a data slicer in the following data recovery circuit.
Increasing mismatch between the actual scale of amplitude and the desired scale of amplitude of the input read signal increases the probability of incorrectly decoding data. Conventional AGC devices used with partial response channels become operative only when a phase locked loop of the data recovery circuit has locked onto the frequency of the components of interest of the read signal. Once lock has occurred, the AGC device compares the digital amplitude value of the sampled read signal with the ideal amplitude value provided by the data slicer. The difference value obtained either is provided as a gain error value, or multiplied by an amount dependent on the ideal value provided by the data slicer, to provide a gain error value. Error values are accumulated over a number of sampling periods to generate a feedback error value which controls the gain of a variable gain amplifier (VGA) within the closed-loop AGC system to scale the amplitude of the read signal.
However, such conventional systems can suffer drawbacks in that any phase or frequency errors in the phase locked loop will result in erroneous gain error values. As the feedback error value will be erroneous as a result of this, correct gain adjustment, or gain lock, of the VGA may not occur, or occur only after many sample clock cycles. Also, such a system cannot be used for initial adjustment of the VGA gain necessary to take the read signal to a magnitude which is suitable for timing recovery by the phase locked loop to occur.
Furthermore, such a conventional AGC system can only produce meaningful gain error values when the actual magnitude of the amplitude of the read signal is close enough to the ideal amplitude magnitude that there are sufficiently few decision errors in the data slicer output to ensure correct phase and frequency lock. The gain need only be a few tens of percent below the ideal gain for gain lock to be unobtainable in, for example, PR(a, b, a) channel data recovery circuits.